Resume
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Download Resume (PDF)Objective
As an M.Tech VLSI postgraduate with a strong foundation in digital electronics and CMOS design and hands-on experience in HDL coding with EDA tools, I am looking to begin my career in the VLSI domain and contribute to the development of efficient and reliable integrated circuits.
Education
M.Tech in VLSI Design
Vellore Institute of Technology (VIT)
Vellore, Tamil Nadu
2025 - Present
GPA 8.15/10.0
B.Tech in Electronics and Communication Engineering
Sree Vidyanikethan Engineering College
Tirupati, Andhra Pradesh
2020 - 2024
CGPA 8.9/10.0
Higher Secondary Education
Narayana Junior College
Nellore, Andhra Pradesh
2018 - 2020
GPA 9.6/10.0
Secondary Education
Nagarjuna Model School
Kadapa, Andhra Pradesh
2018
GPA 10.0/10.0
Technical Skills
Concepts
FSMSTACMOSDigital Electronics
Languages
VerilogSystemVerilog (Basics)
EDA Tools
Cadence VirtuosoModelSimIntel Quartus PrimeSynopsys VCS
Scripting
Basics on TCL
Projects
RISC-V RV32IM SoC Design
Group ProjectDeveloped a 32-bit RISC-V processor using a 2-stage multi-cycle FSM architecture.
VerilogFSM ArchitectureAXI BusGPIO
- *Implemented datapath and control logic with arithmetic, mul/div, load/store, and branch instructions.
- *Interfaced the core with memory and GPIO using an AXI bus.
Hybrid 10T Low Power Full Adder - CMOS VLSI Design
Designed a transistor-level 1-bit hybrid full adder using GDI multiplexer logic in 45nm CMOS.
45nm CMOSMentor Graphics SPICEGDI LogicPDP Analysis
- *Implemented level restoration for full-swing outputs and reduced voltage degradation.
- *Analyzed delay, power, and PDP across supply voltages and process corners.
- *Achieved about 65% transistor reduction and about 80% power-delay-product improvement over conventional CMOS adders.
Asynchronous FIFO Design and Verification
Designed an asynchronous FIFO with independent read and write clock domains.
VerilogCDCGray CodeTestbenches
- *Implemented Gray-coded read/write pointers and double flip-flop synchronizers for safer clock-domain crossing.
- *Verified full and empty conditions using Verilog testbenches.
Achievements
GATE Qualified: 2025 - AIR 6103